FIG. 1 is a block diagram of a conventional asynchronous FIFO memory system 100. Memory system 100 includes dual-port memory 101, which receives input data values at write port 102 and provides output data values at read port 103. FIFO memory system 100 also includes write address counter 104, read address counter 105, comparator 106, and is controlled by write control circuit 108 and read control circuit 109. Write port 102 and read port 103 can be accessed simultaneously. Write address counter 104 and read address counter 105 provide write and read addresses, respectively, to FIFO memory 101. Write and read control circuits 108 and 109 enable write and read operations by enabling write and read address counters 104 and 105 to increment their respective addresses. Write address counter 104 is clocked by a write clock (WCLK) signal, and read address counter 105 is clocked by a read clock (RCLK) signal. The WCLK and RCLK signals are unrelated signals which have different frequencies and/or phases with respect to one another. The asynchronous operation of memory system 100 is well-known in the art.
To assure proper operation of memory system 100, FULL and EMPTY flags are generated when FIFO memory 101 is full and empty, respectively. Comparator 106 provides a FULL flag to write control circuit 108 and an EMPTY flag to read control circuit 109 to report the empty and full conditions. Write control circuit 108 will not initiate write operations when comparator 106 asserts a FULL flag. Similarly, read control circuit 109 will not initiate read operations when comparator 106 asserts an EMPTY flag. Comparator 106 generates the FULL and EMPTY flags by comparing the write address from write address counter 104 with the read address from read address counter 105. When a write operation results in equality of the read and write addresses, FIFO memory 101 is full, and comparator 106 asserts a FULL flag. When a read operation results in equality of the read and write addresses, FIFO memory is empty, and comparator 106 asserts an EMPTY flag.
Comparator 106 can perform a reliable comparison only after the read and write addresses have been synchronized with a common clock signal. Thus, the read address can be synchronized with the WCLK signal, and the comparison can be performed in synchronism with the WCLK signal. Alternatively, the write address can be synchronized with the RCLK signal, and the comparison can be performed in synchronism with the RCLK signal.
For purposes of illustration, comparator 106 is connected to receive the WCLK signal, and the read address is synchronized with the WCLK signal. Comparator 106 compares the write and read addresses on each rising edge of the WCLK signal. In memory system 100, write operations are capable of proceeding at full speed because, after each write operation, comparator 106 immediately determines whether FIFO memory 101 is full. The FULL flag may be asserted unnecessarily based on the synchronization latency which exists between the incrementing of the read address counter 105 and the rising edge of the WCLK signal. For example, the FULL flag can be erroneously asserted when a read operation (which would cause FIFO memory 101 to be not full) occurs immediately prior to a write operation, but this read operation is not recorded by the comparator 106 because of the synchronization latency. The erroneous assertion of the FULL flag does not result in the destruction of data values within FIFO memory 101. Rather, the erroneous FULL flag prevents FIFO memory 101 from being filled to its maximum capacity until after the synchronization latency expires. Loss of performance is only experienced when FIFO memory 101 is within a few data values of being full.
In contrast, read operations cannot be performed at full speed. Performance is always degraded for read operations because read control circuit 109 must wait for comparator 106 to generate the EMPTY flag each time read address counter 105 is incremented. Each time that read address counter 105 is incremented, the new read address must be synchronized to the WCLK signal within comparator 106. The new read address must then be compared to the current write address within comparator 106, and the result (empty or not empty) must be re-synchronized to the RCLK signal and provided to the read control logic. Both of these synchronization operations inevitably incur latency.
If a read operation is performed when FIFO memory 101 is empty, an erroneous data value will be read. In addition, the next data value written into FIFO memory 101 will be lost because read address counter 105 was improperly incremented to read the erroneous data value. Potentially, the erroneous read operation could prevent the EMPTY flag from being properly asserted even after the synchronization latency period. In order to prevent such erroneous operation, the read operation must be delayed until the synchronization issues have been resolved. Therefore, the synchronization latency introduces an operation latency within the FIFO memory 101.
It would therefore be desirable to have an asynchronous FIFO memory which is capable of performing both read and write operations with minimal operation latency.